UVM 基礎觀念
架構、資料流與資料型態

program automatic test;

  import uvm_pkg::*;
  `include "uvm_macros.svh"        // 沒有這行，`uvm_info / `uvm_component_utils 都不能用

  class hello_world extends uvm_test;
    `uvm_component_utils(hello_world)          // 註冊到 factory

    function new(string name = "hello_world", uvm_component parent = null);
      super.new(name, parent);
    endfunction

    virtual task run_phase(uvm_phase phase);
      phase.raise_objection(this);             // 舉手：我還沒做完，別結束模擬
      #50;
      `uvm_info("TEST", "Hello World!", UVM_MEDIUM)
      phase.drop_objection(this);              // 放手：可以結束了
    endtask
  endclass

  initial begin
    run_test("hello_world");                   // 啟動 UVM，指定要跑哪個 test
  end

endprogram

interface adder_intf (input logic clk, input logic rst_n);
  logic [6:0] in1;
  logic [6:0] in2;
  logic [7:0] out;

  modport dut (input in1, input in2, output out);              // DUT：吃輸入、吐輸出

  modport drv (output in1, output in2, input out,              // Driver：只能寫 in1/in2
               input clk, input rst_n);

  modport mon (input in1, input in2, input out,                // Monitor：純觀察，全 input
               input clk, input rst_n);
endinterface

virtual function void build_phase(uvm_phase phase);
  super.build_phase(phase);
  if (is_active == UVM_ACTIVE) begin              // 只有 Active 才需要出刺激
    m_drv = driver_c::type_id::create("m_drv", this);
    m_sqr = uvm_sequencer#(trans_c)::type_id::create("m_sqr", this);
  end
  m_mon = monitor_c::type_id::create("m_mon", this);   // Monitor 永遠要建
endfunction

virtual function void connect_phase(uvm_phase phase);
  super.connect_phase(phase);
  if (is_active == UVM_ACTIVE)
    m_drv.seq_item_port.connect(m_sqr.seq_item_export);   // 沒建就別連，否則 null handle
endfunction

virtual task run_phase(uvm_phase phase);
  trans_c m_trans;

  adder_vif.in1 <= '0;                    // reset 期間先把訊號歸零
  adder_vif.in2 <= '0;
  wait (adder_vif.rst_n === 1'b1);        // 等 reset 放開才開始工作

  forever begin
    seq_item_port.get_next_item(m_trans);       // ← 阻塞：沒東西就在這等
    @(posedge adder_vif.clk);                   //   對齊時脈
    adder_vif.in1 <= m_trans.in1;               //   非阻塞賦值，避免 race
    adder_vif.in2 <= m_trans.in2;
    `uvm_info("DRV", $sformatf("Drive in1=%0d, in2=%0d",
              m_trans.in1, m_trans.in2), UVM_LOW)
    seq_item_port.item_done();                  // ← 告訴 sequencer：這筆做完了
  end
endtask

virtual task run_phase(uvm_phase phase);
  trans_c m_trans;
  logic [6:0] in1_q, in2_q;      // 暫存這一拍的輸入
  int idx = 0;

  wait (adder_vif.rst_n === 1'b1);
  @(posedge adder_vif.clk);
    #1;                          // ★ 讓 NBA 區更新完再讀，避開取樣 race

  forever begin
    in1_q = adder_vif.in1;       // cycle N：記住輸入
    in2_q = adder_vif.in2;
    @(posedge adder_vif.clk);
    #1;
    m_trans = trans_c::type_id::create($sformatf("mon_trans_%0d", idx++), this);
    m_trans.in1 = in1_q;         // cycle N 的輸入
    m_trans.in2 = in2_q;
    m_trans.out = adder_vif.out; // cycle N+1 的輸出 ← 這才是同一筆交易
    m_mon_port.write(m_trans);   // 廣播
  end
endtask

class trans_c extends uvm_sequence_item;
  rand logic [6:0] in1;        // rand：randomize() 時會被灌值
  rand logic [6:0] in2;
       logic [7:0] out;        // 沒有 rand：這是 DUT 給的，不是我們產生的

  function new(string name = "");
    super.new(name);
  endfunction

  `uvm_object_utils_begin(trans_c)      // begin/end 版本才能塞 field macro
    `uvm_field_int(in1, UVM_DEFAULT)
    `uvm_field_int(in2, UVM_DEFAULT)
    `uvm_field_int(out, UVM_DEFAULT)
  `uvm_object_utils_end
endclass

virtual task main_phase(uvm_phase phase);
  sequence_c m_seq;
  int iter = 0;

  phase.raise_objection(this);            // ← 舉手：別結束

  // 一直送 sequence，直到覆蓋率達標或跑滿次數
  while (m_env.m_cov.covgrp.get_coverage() < cov_target && iter < max_iter) begin
    m_seq = sequence_c::type_id::create($sformatf("seq_%0d", iter), this);
    m_seq.start(m_env.m_agt.m_sqr);       // ← 把 sequence 掛到 sequencer 上跑
    iter++;
  end

  phase.phase_done.set_drain_time(this, 20ns);   // 多留 20ns 給管線裡的殘料流完

  phase.drop_objection(this);             // ← 放手：可以收工了
endtask

virtual function void connect_phase(uvm_phase phase);
  super.connect_phase(phase);
  m_agt.m_mon.m_mon_port.connect(m_scr.m_scr_imp);          // → scoreboard
  m_agt.m_mon.m_mon_port.connect(m_cov.analysis_export);    // → coverage
endfunction

uvm_tlm_analysis_fifo #(trans_c) drv_fifo;   // 存 driver 送來的「輸入」
uvm_tlm_analysis_fifo #(trans_c) mon_fifo;   // 存 monitor 送來的「輸出」

virtual task run_phase(uvm_phase phase);
  trans_c drv_tr, mon_tr;
  logic [7:0] expected;

  forever begin
    drv_fifo.get(drv_tr);                 // blocking：沒資料就在這等
    mon_fifo.get(mon_tr);                 // 兩邊各取一筆，自動配對
    expected = reference_model(drv_tr);   // expected = drv_tr.in1 + drv_tr.in2

    if (mon_tr.out === expected) pass_cnt++;
    else `uvm_error("SCR", $sformatf("FAIL: expected %0d, got %0d", expected, mon_tr.out))
  end
endtask

initial begin
  uvm_config_db#(virtual adder_intf.drv)::set(null,
      "uvm_test_top.m_env.m_agt.m_drv", "adder_vif", intf);

  uvm_config_db#(virtual adder_intf.mon)::set(null,
      "uvm_test_top.m_env.m_agt.m_mon", "adder_vif", intf);

  run_test("test");        // set 一定要在 run_test 之前
end

virtual adder_intf.drv adder_vif;          // 型態要跟 set 端一模一樣

virtual function void build_phase(uvm_phase phase);
  super.build_phase(phase);
  if (!uvm_config_db#(virtual adder_intf.drv)::get(this, "", "adder_vif", adder_vif))
    `uvm_fatal("DRV", "Unable to get interface adder_vif (drv)")
endfunction

// (1) 繼承出一個新的 transaction，加一條約束
class trans_in1_3_c extends trans_c;
  `uvm_object_utils(trans_in1_3_c)          // ★ 一定要註冊，否則 override 不生效

  function new(string name = "");
    super.new(name);
  endfunction

  constraint in1_eq_3 { in1 == 3; }         // 把 in1 釘死成 3
endclass

// (2) 在 test 的 build_phase 最前面設 override
virtual function void build_phase(uvm_phase phase);
  set_type_override_by_type(
    trans_c::get_type(),                    // 原本要生的
    trans_in1_3_c::get_type()               // 實際生出來的
  );

  super.build_phase(phase);                 // ← override 必須在這行之前
  m_env = env_c::type_id::create("m_env", this);

  uvm_factory::get().print();               // (3) 印出 Type Overrides 表驗證
endfunction

class cov_coll_c extends uvm_subscriber #(trans_c);
  `uvm_component_utils(cov_coll_c)

  trans_c m_trans;                    // ★ covergroup 取樣的來源是這個成員變數

  covergroup covgrp;
    option.per_instance = 1;          // 每個實體各自統計

    cp1: coverpoint m_trans.in1 {
      bins in1_min    = {0};          // 單一值
      bins in1_max    = {127};
      bins in1_low[]  = {[1:63]};     // [] = 自動展開成 63 個 bin
      bins in1_high[] = {[64:126]};
    }
    cp2: coverpoint m_trans.in2 { /* 同上 */ }
    cp3: coverpoint m_trans.out {
      bins low  = {[0:127]};
      bins high = {[128:254]};        // 有沒有測到「會進位」的情況
    }
    cp1xcp2: cross cp1, cp2;          // 交叉：兩邊的組合有沒有走遍
  endgroup

  function new(string name = "", uvm_component parent);
    super.new(name, parent);
    covgrp = new();                   // ★ covergroup 必須在 new() 裡實體化
  endfunction

  virtual function void write(trans_c t);   // monitor 每廣播一筆就進來一次
    m_trans = t;                            // 先更新成員變數
    covgrp.sample();                        // 再取樣
  endfunction
endclass

while (m_env.m_cov.covgrp.get_coverage() < cov_target && iter < max_iter) begin
  m_seq = sequence_c::type_id::create($sformatf("seq_%0d", iter), this);
  m_seq.start(m_env.m_agt.m_sqr);
  iter++;
end

if (iter >= max_iter)
  `uvm_warning("TEST", "Hit max_iter before reaching coverage target")

// Setup phase：PSEL=1、PENABLE=0，放上位址/方向/寫資料
@(posedge apb_vif.clk);
apb_vif.psel    <= 1'b1;
apb_vif.penable <= 1'b0;
apb_vif.pwrite  <= m_trans.pwrite;
apb_vif.paddr   <= m_trans.paddr;
apb_vif.pwdata  <= m_trans.pwdata;

// Access phase：下一拍才把 PENABLE 拉高
@(posedge apb_vif.clk);
apb_vif.penable <= 1'b1;

// Wait state：PREADY=0 就繼續等，期間不能改 PADDR/PWRITE/PWDATA
while (!apb_vif.pready)
  @(posedge apb_vif.clk);

if (apb_vif.psel && apb_vif.penable && apb_vif.pready) begin
  s_pwrite = apb_vif.pwrite;      // (a) 先鎖存刺激欄位
  s_paddr  = apb_vif.paddr;
  s_pwdata = apb_vif.pwdata;

  @(posedge apb_vif.clk);
  #1;                             // (b) 等 DUT 用 NBA 寫的 prdata/pslverr 穩定

  m_trans = trans_c::type_id::create($sformatf("mon_trans_%0d", idx++), this);
  m_trans.pwrite  = s_pwrite;
  m_trans.paddr   = s_paddr;
  m_trans.pwdata  = s_pwdata;
  m_trans.prdata  = apb_vif.prdata;   // (c) 再補上 DUT response
  m_trans.pslverr = apb_vif.pslverr;
end

// assertion：PENABLE 只能在「前一拍已經是 Setup phase」之後才拉高
property apb_penable_after_psel;
  @(posedge clk) disable iff (!rst_n)
    $rose(intf.penable) |->
      (intf.psel && $past(intf.psel && !intf.penable));
endproperty

apb_penable_after_psel_a : assert property (apb_penable_after_psel)
  else `uvm_error("APB_ASSERT", "PENABLE asserted without previous APB setup phase")

// cover property：確認測試中真的走過 Setup → Access 這條路
property apb_setup_to_access;
  @(posedge clk) disable iff (!rst_n)
    (intf.psel && !intf.penable) ##1 (intf.psel && intf.penable);
endproperty

apb_setup_to_access_cp : cover property (apb_setup_to_access);